MT-008 tutorial converting oscillator phase noise to time jitter by walt kester introduction a low aperture jitter specification of an adc is critical to achieving high levels of signal-to- noise ratios (snr). (see references 1, 2, and 3) . adcs are available with aperture jitter specifications as low as 60-fs rms ( ad9445 14-bits @ 125 msps and ad9446 16-bits @ 100 msps). extremely low jitter sampling clocks must therefore be utilized so that the adc performance is not degraded, because the total j itter is the root-sum-s quare of the internal converter aperture jitter and the external sampli ng clock jitter. however, oscillators used for sampling clock generation are more often specified in terms of phase noise rather than time jitter. the purpose of this discussion is to develop a simple method for converting oscillator phase noise into time jitter. phase noise defined first, a few definitions are in order. figure 1 shows a typical output frequency spectrum of a non-ideal oscillator (i.e., one that has jitter in the ti me domain, corresponding to phase noise in the frequency domain). the spectrum shows the noise power in a 1-hz bandwidth as a function of frequency. phase noise is define d as the ratio of the noise in a 1-hz bandwidth at a specified frequency offset, f m , to the oscillator signal amplitude at frequency f o . phase noise (dbc/hz) f o f "close-in" phase noise broadband phase noise (limits frequency resolution) (reduces snr) 1hz bw f m figure 1: oscillator power sp ectrum due to phase noise rev.a, 10/08, wk page 1 of 10
MT-008 the sampling process is basically a multiplication of the sampling clock and the analog input signal. this is multiplication in the time domai n, which is equivalent to convolution in the frequency domain. therefore, the spectrum of th e sampling clock oscillato r is convolved with the input and shows up on the fft output of a pure sinewave input signal (see figure 2). ideal adc analog input, f o dsp f s f o f s f o ideal sinewave input sampling clock with phase noise fft output snr for ideal adc with n n (measured from dc to f s /2) close-in broadband snr = 20log 10 1 2 f o t j f f f figure 2: effect of sampling clock phase noise ideal digitized sinewave the "close-in" phase noise will "smear" the fundamental signal in to a number of frequency bins, thereby reducing the overall spectral resolution. the "broadband" phase noise will cause a degradation in the overall snr as pr edicted by eq. 1 (reference 1 and 2): ? ? ? ? ? ? ? ? = j 10 tf2 1 log20 snr . eq. 1 it is customary to characterize an oscillator in terms of its single-sideba nd phase noise as shown in figure 3, where the phase noise in dbc/hz is plotted as a function of frequency offset, f m , with the frequency axis on a log scale. note the ac tual curve is approximate d by a number of regions, each having a slope of 1/f x , where x = 0 corresponds to the "w hite" phase noise region (slope = 0 db/decade), and x = 1 corresponds to the "flicker" phase noise region (slope = ?20 db/decade). there are also regions where x = 2, 3, 4, and thes e regions occur progressively closer to the carrier frequency. page 2 of 10
MT-008 phase noise (dbc/hz) frequency offset, f m , (log scale) 1 f 1 f 2 1 f 3 "white" phase noise "flicker" phase noise 1 f corner frequency figure 3: oscillator phase noise in dbc/hz vs. frequency offset note that the phase noise curve is somewhat anal ogous to the input voltage noise spectral density of an amplifier. like amplifie r voltage noise, low 1/f corner fr equencies are highly desirable in an oscillator. we have seen that oscillators are typically specified in terms of phase noise, but in order to relate phase noise to adc performance, the phase noise must be converted into jitte r. in order to make the graph relevant to modern adc applications, the oscillator frequency (sampling frequency) is chosen to be 100 mhz for discussion purposes, a nd a typical graph is sh own in figure 4. notice that the phase noise curve is approximated by a number of individual line segments, and the end points of each segment are defined by data points. 10k 100k 1m 10m 100m 1g frequency offset (hz) rms phase jitter (radians) 2? 10 a/10 area = integrated phase noise power (dbc) rms jitter (seconds) 2 f o f o = oscillator frequency (100mhz) 2 f o = 200mhz phase noise (dbc/hz) f m a = integrate to 2?10 a/10 a1 a2 a3 a4 a = 10 log 10 (a1 + a2 + a3 + a4) figure 4: calculating jitter from phase noise page 3 of 10
MT-008 converting phase noise to jitter the first step in calculating the equivalent rms jitter is to obtain the integrated phase noise power over the frequency range of interest, i.e., the ar ea of the curve, a. the curve is broken into a number of individual areas (a1, a2, a3, a4), each defined by two data points. generally speaking, the upper frequency range for the integration should be twice the sampling frequency, assuming there is no filtering be tween the oscillator and the adc input. this approximates the bandwidth of the adc sampling clock input. selecting the lower frequency for the integration also requires some judgment. in theory, it should be as low as possible to get the true rms jitter. in practice, however, the oscillator specifications generally will not be given for o ffset frequencies less than 10 hz, or so?however, this will certainly give accurate enough result s in the calculations. a lower frequency of integration of 100 hz is reasonable in most cases, if that specification is available. otherwise, use either the 1-khz or 10-khz data point. one should also consider that the "close-in" ph ase noise affects the sp ectral resolution of the system, while the broadband noise affects the over all system snr. probabl y the wisest approach is to integrate each area separately as explai ned below and examine the magnitude of the jitter contribution of each area. the low frequency cont ributions may be negligible compared to the broadband contribution if a crystal oscillator is used. other types of oscillators may have significant jitter contributions in the low frequenc y area, and a decision mu st be made regarding their importance to the overall system frequency resolution. the integration of each individual area yields individual power ratios. the individual power ratios are then summed and converted back into dbc. once the integrated phase noise power is known, the rms phase jitter in radi ans is given by the equation (s ee references 3-7 for further details, derivations, etc.), 10/a 102)radians(jitterphaserms ?= , eq. 2 and dividing by 2 f o converts the jitter in radi ans to jitter in seconds: o 10/a f2 102 )onds(secjitterphaserms ? = . eq. 3 it should be noted that comput er programs and spreadsheets are available online to perform the integration by segments and calculate the rms jitter, thereby greatly simplifying the process (references 8, 9). figure 5 shows a sample calculation which assu mes only broadband phase noise. the broadband phase noise chosen of ?150 dbc/hz represents a reasonably good signal ge nerator specification, so the jitter number obtained re presents a practical situation. the phase noise of ?150 dbc/hz (expressed as a ratio) is multiplied by the bandw idth of integration (200 mhz) to obtain the integrated phase noise of ?67 dbc. note that this multiplication is equivalent to adding the page 4 of 10
MT-008 quantity 10 log 10 [200 mhz ? 0.01 mhz] to the phase noise in dbc/hz. in practice, the lower frequency limit of 0.01 mhz can be dropped from the calculation, as it does not affect the final result significantly. a total rms jitter of a pproximately 1 ps is obtained using eq. 3. 10k 100k 1m 10m 100m 1g frequency offset (hz) f o = oscillator frequency (100mhz) 2 f o = 200mhz phase noise (dbc/hz) f m integrate to a ?150 rms phase jitter (radians) 2?10 = 6.32 10 ?4 radians a/10 rms jitter (seconds) = rms phase jitter (radians) 2 f o a = ?150dbc + 10 log 10 200 10 6 ?0.01 10 6 = ?150dbc + 83db = ?67dbc = 1ps figure 5: sample jitter calculat ion assuming broadband phase noise crystal oscillators generally offer the lowest po ssible phase noise and jitter, and some examples are shown for comparison in figu re 6. all the oscillators show n have a typical 1/f corner frequency of 20 khz, and the phase noise therefor e represents the white phase noise level. the two wenzel oscillators are fixed- frequency and represent excellent performance (reference 9). it is difficult to achieve this level of performan ce with variable frequenc y signal generators, as shown by the ?150 dbc specification for a relatively high quality generator. ? wenzel uln series* ?174dbc/hz @ 10khz+ ? wenzel sprinter series, ?165dbc/hz @ 10khz+ ? high quality signal generator ?150dbc/hz @ 10khz+ z thermal noise floor of resistive source in a matched system @ +25c = ?174dbm/hz z 0dbm = 1mw = 632mv p-p into 50 z * an oscillator with an output of +13dbm (2.82v p-p) into 50 with a phase noise of ?174dbc/hz has a noise floor of +13dbm ? 174dbc = ?161dbm, 13db above the thermal noise floor (wenzel uln and sprinter series specifications and pricing used with permission of wenzel associates) figure 6: 100-mhz oscillator broadband phase noise floor comparisons (wenzel uln and sprinter series specifications and pricing used with permission of wenzel associates) page 5 of 10
MT-008 at this point, it should be noted that there is a th eoretical limit to the noise floor of an oscillator determined by the thermal noise of a matched s ource: ?174 dbm/hz at + 25c. therefore, an oscillator with a +13-dbm output into 50 (2.82-v p-p) with a phase noise of ?174 dbc/hz has a noise floor of ?174 dbc + 13 dbm = ?161 dbm. this is the case for the wenzel uln series as shown in figure 6. figure 7 shows the jitter calculations from the two wenzel crystal oscillators. in each case, the data points were taken directly for the manufacturer's data sheet . because of the low 1/f corner frequency, the majority of the jitter is due to the "white" phase noise area. the calculated values of 64 fs (uln-series) and 180 fs represent extrem ely low jitter. for informational purposes, the individual jitter cont ributions of each area have been labeled separately. the total jitter is the root-sum-square of the indi vidual jitter contributors. 100 1k 10k 100k 1m 10m ?120 ?130 ?140 ?150 ?160 ?170 ?180 (?125dbc/hz, 100hz) (?150dbc/hz, 1khz) (?174dbc/hz, 10khz) (?174dbc/hz, 200mhz) 0.01ps 0.002ps 0.063ps total rms jitter = 0.064ps frequency offset (hz) phase noise (dbc/hz) 100 1k 10k 100k 1m 10m ?120 ?130 ?140 ?150 ?160 ?170 ?180 (?120dbc/hz, 100hz) (?150dbc/hz, 1khz) (?165dbc/hz, 10khz) (?165dbc/hz, 200mhz) 0.02ps 0.003ps 0.18ps total rms jitter = 0.18ps frequency offset (hz) phase noise (dbc/hz) wenzel standard 100mhz-sc ultra low noise (uln) crystal oscillator wenzel standard 100mhz-sc sprinter crystal oscillator 100m 100m figure 7: jitter calculations for low noise 100-mhz crystal oscillators (phase noise data used with pe rmission of wenzel associates) in system designs requiring low jitter sampling clocks, the costs of low noise dedicated crystal oscillators is generally prohibitive. an alternative solution is to use a phase-locked-loop (pll) in conjunction with a voltage-controll ed oscillator to "clean up" a no isy system clock as shown in figure 8. there are many good references on pll design (see references 10-13, for example), and we will not pursue that topic further, other th an to state that using a narrow bandwidth loop filter in conjunction with a voltage-controlled cr ystal oscillator (vcxo) typically gives the lowest phase noise. as shown in figure 8, the pll tends to reduce the "close-in" phase noise while at the same time, reducing the overall pha se noise floor. further reduction in the white noise floor can be obtained by following the p ll output with an appr opriate bandpass filter. page 6 of 10
MT-008 phase detector charge pump loop filter bpf adc sampling clock noisy clock f s f s f s f s vcxo divider adf4001, or adf41xx-series figure 8: using a phase-loc ked loop (pll) and bandpass filter to condition a noisy clock source the effect of enclosing a free-r unning vco within a pll is show n in figure 9. notice that the "close-in" phase noise is reduced sign ificantly by the action of the pll. figure 9: phase noise for a free-runni ng vco and a pll-connected vco page 7 of 10
MT-008 analog devices offers a wide portfolio of fre quency synthesis products, including dds systems, n, and fractional-n plls. for example, the adf4360 family are fully integrated plls complete with an internal vco. with a 10-khz bandw idth loop filter, the phase noise of the adf4360-1 2.25-ghz pll is shown in figure 10, and the line -segment approximation a nd jitter calculations shown in figure 11. note that the rms jitter is only 1.57 ps, even with a non-crystal vco. phase noise (dbc/hz) figure 10: phase noise for adf4360-1 2.25-ghz pll with loop filter bw = 10 khz 100 1k 10k 100k 1m 10m 100m 1g ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 4.5g (?82dbc/hz, 100hz) (?77dbc/hz, 10khz) (?112dbc/hz, 100khz) (?134dbc/hz, 1mhz) (?146dbc/hz, 10mhz) (?146dbc/hz, 4.5ghz) 0.28ps 0.89ps 0.07ps 0.03ps 0.34ps total rms jitter = 1.57ps phase noise (dbc/hz) frequency offset (hz) (?80dbc/hz, 1khz) ?70 1.21ps figure 11: line segment approx imation to adf436 0-1, 2.25-ghz pll phase noise showing jitter page 8 of 10
MT-008 historically, pll design relied heavily on textbooks and application notes to assist in the design of the loop filter, etc. now, w ith analog devices free downloadable adisimpll ? software, pll design is much easier. to start, choose a circu it by entering the desired output frequency range, and select a pll, vco, and a crystal reference. once the loop filter configurat ion has been selected, the circuit can be analyzed and optim ized for phase noise, phase margin, gain, spur levels, lock time, etc., in both the frequency and time domain. the program also performs the rms jitter calculation based on the pll phase noise, thereby allowing the evaluation of the final pll output as a sampling clock. summary sampling clock jitter can be di sastrous to the snr performa nce of high performance adcs. although the relationship between snr and jitter is we ll known, most oscillators are specified in terms of their phase noise. this article has show n how to convert phase noi se into jitte r so that the snr degradation can be easily calculated. although not as good as relatively expensive stan d alone crystal oscillators, modern plls using crystal vcos (along with suitable filtering) can achieve jitter performance suit able for all but the most demanding requirements. the entire problem of clock distribution has be come much more critical because of low jitter requirements. analog devices is now offering a line of clock di stribution ics to serve these needs (www.analog.com/clocks). page 9 of 10
page 10 of 10 MT-008 references 1. brad brannon, " aperture uncertainty and adc system performance, " application note an-501 , analog devices, download at http://www.analog.com. 2. bar-giora goldberg, "the effects of cl ock jitter on data conversion devices," rf design , august 2002, pp. 26-32, http://www.rfdesign.com. 3. ulrich l. rohde, digital pll frequency synthesizers, theory and design , prentice-hall, 1983, isbn 0- 13-214239-2, all of chapter 2 and pp. 411-418 for computer analysis. 4. joseph v. adler, "clock-source jitter: a clear understanding aids oscillator selection," edn , february 18, 1999, pp. 79-86, http://www.ednmag.com. 5. neil roberts, "phase noise and jitter ? a primer for digital designers," eedesign , july 14, 2003, http://www.eedesign.com. 6. boris drakhlis, "calculate oscillator jitter by using phase-noise analysis part 1," microwaves and rf , january 2001, p. 82, http://www.mwrf.com. 7. boris drakhlis, "calculate oscillator jitter by using phase-noise analysis part 2," microwaves and rf , february 2001, p. 109, http://www.mwrf.com. 8. raltron electronics corporation, 10651 northwest 19th street, miami, florida 33172, tel: (305) 593- 6033, http://www.raltron.com . (see "convert ssb phase noise to jitter" under "engineering design tools"). 9. wenzel associates, inc., 2215 kramer lane, austin, texas 78758, tel: (512) 835-2038, http://www.wenzel.com (see "allan variance from phase noise" under "spreadsheets"). 10. mike curtin and paul o'brien, " phase-locked loops for high-frequenc y receivers and transmitters, part 1 , analog dialogue 33-3, 1999, http://www.analog.com. 11. mike curtin and paul o'brien, " phase-locked loops for high-frequenc y receivers and transmitters, part 2 , analog dialogue 33-5, 1999, http://www.analog.com. 12. r. e. best, phase-locked loops: theory, design and applications, fourth edition , mcgraw-hill, 1999, isbn 0071349030. 13. f. m. gardner, phaselock techniques, second edition , john wiley, 1979, isbn 0471042943. copyright 2009, analog devices, inc. all rights reserved. analog devices assumes no responsibility for customer product design or the use or application of customers? products or for any infringements of patents or rights of others which may result from analog devices assistance. all trad emarks and logos are property of their respective holders. information furnished by analog devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by analog devices regarding technical accuracy and topicality of the content provided in analog devices tutorials.
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